1. Field of the Invention
This invention relates generally to a four-transistors static-random-access-memory (SRAM) memory cell that is suitable for apply to the lower power product, that has a reduced size as compared with conventional SRAM cells, or both.
2. Description of the Prior Art
To meet customer demand for small size and low power products, manufacturers are producing newer integrated circuits (ICs) that operate with lower supply voltages and that include smaller internal subcircuits such as memory cells. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include one or more SRAM cells for data storage. SRAMs cells are popular because they operate at a higher speed than dynamic random-access-memory (DRAM) cells, and as long as they are powered, they can store data indefinitely, unlike DRAM cells, which must be periodically refreshed.
Conventional structure of SRAM cell is a six-transistors SRAM cell, which means six transistors are used to form a SRAM cell. In general, advantages of six-transistors SRAM cell at least include high speed and possibility of low supply voltage. By unfortunately, one unavoidable disadvantage is that area of six-transistor SRAM cell is large. Clearly, when size of semiconductor device is continually decreased, the disadvantage is more serious and it is desired to overcome the disadvantage by either improving structure of six-transistors SRAM cell or providing a new SRAM cell.
One way to reduce area of six-transistors SRAM cell is to make structure to be three-dimensional. However, to solidity structure of six-transistors SRAM cell also complicates relative fabrication and configuration of six-transistors SRAM cell. In other words, this way is not an efficient way.
Another popular way to reduce area of six-transistors SRAM cell is application of four-transistors SRAM. Although there are numerous varieties of four-transistors SRAM cell, the basic structure of four-transistors SRAM cell can be divided into two access transistors and two pull-down transistors. Herein, as usual, one access transistor and one pull-down transistor are used to storage data, another access transistor and another pull-down transistor are used to control reading/writing processes. Clearly, owing to number of used transistor is decreased, occupied area of four-transistors SRAM cell is less than six-transistors SRAM cell. Thus, four-transistors SRAM cell is more suitable for ICs whenever sizes of ICs are reduced, even four-transistors also meets some disadvantages such as higher off-state leakage current of PMOS. More introduction of four-transistors SRAM cell can be provided by referring to U.S. Pat. No. 5943269, U.S. Pat. No. 6091628, U.S. Pat. No. 6044011, U.S. Pat. No. 011726, U.S. Pat. No. 5751044 and so on.
One ordinary circuit diagram of four-transistor SRAM cell is shown in FIG. 1. The four-transistor SRAM cell, which is a loadless four-transistors SRAM cell, comprises first transistor 11, second transistor 12, third transistor 13, fourth transistor 14, first word line terminal 15, second word line terminal 16, first bit line terminal 17 and second bit line terminal 18. In detail, source of first transistor 11 is coupled to first bit line terminal 17, gate of first transistor 11 coupled to first word line terminal 15, drain of first transistor 11 is coupled to gate of fourth terminal 14, source of second transistor 12 is coupled to second bit line terminal 18, gate of second transistor is coupled to second word line terminal 16, drain of second transistor 12 is coupled to gate to third transistor 13. More over, drain of fourth transistor 14 and drain of third transistor 13 are coupled to a common voltage point 19, such as electrical zero point, each of both first bit line terminal 17 and second bit line terminal 18 is coupled to a corresponding bit line, and both first word line terminal 15 and second word line terminal 16 are coupled to the same word line.
Because leakage current of first transistor 11 and leakage current of second transistor 12 are not absolute zero, especially when first transistor 11/second transistor 12 are P-type transistor. An unavoidable shortage is that because first word line terminal 15 and second word line terminal 16 by same word line, third transistor 13 is turn on by leakage current of second transistor 12 whenever both first transistor 11 and second transistor 12 are not totally turn off. Thus, whenever current is sent to first bit line terminal 17 (means data is storaged), owing to both first transistor 11 and third transistor 13 are not totally turn off now, current continually flow through first transistor 11 and third transistor into common voltage point 19. Significantly, continuous flow of current requires continuous supply of current, then stand-by current of the four-transistor SRAM cell is not negligible and the four-transistor SRAM cell is less suitable for low power product.
Therefore, although four-transistor SRAM is physically smaller and is suitable for some ICs that include smaller internal subcircuits, it still is not enough suitable for operation at low supply power. Then, improvement of four-transistor SRAM is desired to let it is suitable for low power product.
One main object of the invention is to present a four-transistors SRAM cell which is suitable for low power product.
Another important object of the invention is to present a four-transistors SRAM cell which is easy to be produced, especially the differences between the present four-transistors SRAM cell and other well-known four-transistors SRAM cell are not too large to let fabrication of the present four-transistors SRAM cell is strongly different from fabrication of the well-known four-transistors SRAM cell.
Still an essential object of the invention is to present a four-transistors SRAM cell by limiting circuit diagram of the present four-transistors SRAM cell but not limiting structure of the present four-transistors SRAM cell. In other words, there are various structures of the present four-transistors SRAM cell.
One embodiment of the invention is a memory cell, a fourth transistor SRAM cell, which comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor.